The present invention relates to a functional block for integrated circuit (hereinafter, simply referred to as an xe2x80x9cIC functional blockxe2x80x9d) implemented as a macro cell including a self-diagnosis circuit for detecting a fault between functional blocks, for example. The present invention also relates to a semiconductor integrated circuit that has been designed using the IC functional block and to respective methods for testing and designing the semiconductor integrated circuit.
In recent years, demand for designing a semiconductor integrated circuit more efficiently by implementing the circuit as a combination of functional blocks such as macro cells has been increasing. If a semiconductor integrated circuit is designed by combining a plurality of functional blocks with each other, however, there arises a problem in how to test a signal line interconnecting these functional blocks together. To solve this problem, according to a conventional technique, the operations of a pair of functional blocks interconnected are tested by externally supplying test data for operating these functional blocks. According to another conventional technique, scan circuits are provided for an output section of a functional block on the transmitting end and for an input section of an associated functional block on the receiving end, respectively. And the functional block on the transmitting end is tested through a scanning operation.
Hereinafter, a conventional method for testing a semiconductor integrated circuit made up of a plurality of functional blocks will be described with reference to the drawings.
FIG. 25 illustrates a simplified block configuration for a semiconductor integrated circuit to exemplify a method for testing the semiconductor integrated circuit as a first prior art example. As shown in FIG. 25, the semiconductor integrated circuit 500 includes first and second functional blocks 501 and 502, for example. A plurality of inter-block signal lines 503 are provided between the first and second functional blocks 501 and 502. External input terminals 504, through which parallel data can be input, are provided for the input end of the first functional block 501. External output terminals 505, through which parallel data can be output, are provided for the output end of the second functional block 502.
A test is carried out between these functional blocks in the following manner. First, a test data pattern is input through the external input terminals 504. The first functional block 501 supplies a result of an operation, which has been performed responsive to the test data pattern received, as an output signal onto the inter-block signal lines 503. Next, an output signal, which might have been affected by a fault during the propagation through the inter-block signal lines 503, is input to the second functional block 502. The second functional block 502 outputs a result of an operation, which has been performed responsive to the input signal, through the external output terminals 505. Based on this result of operation, it is determined whether or not there is any fault, thereby testing the semiconductor integrated circuit 500. A similar technique is also applicable to even a semiconductor integrated circuit including a multiplicity of functional blocks. That is to say, a test data pattern is input to each of these functional blocks, and it is decided whether the output result thereof is correct or erroneous.
FIG. 26 illustrates a simplified block configuration for a semiconductor integrated circuit to exemplify another method for testing the semiconductor integrated circuit as a second prior art example. As shown in FIG. 26, the semiconductor integrated circuit 510 includes first and second functional blocks 511 and 512, for example. A plurality of interblock signal lines 513 are provided between the first and second functional blocks 511 and 512. A scan-in pin 514, through which scan data is input, is provided for the input end of the first functional block 511. A scan-out pin 515, through which the scan data is output, is provided for the output end of the second functional block 512. At the output end of the first functional block 511, a shift register 516, which can output data in parallel to the outside, is provided. At the input end of the second functional block 512, a shift register 517, which can receive data in parallel from the outside, is provided. In this example, the scan-in pin 514, shift registers 516 and 517 and scan-out pin 515 are connected in series to each other.
A testing method is performed in the following manner. First, a test data pattern is scanned in through the scan-in pin 514 while being shifted by the shift register 516. The first functional block 511 supplies a result of an operation, which has been performed responsive to the test data pattern received, as an output signal onto the inter-block signal lines 513. Next, an output signal, which might have been affected by a fault during the propagation through the interblock signal lines 513, is input to the shift register 517 of the second functional block 512. The second functional block 512 shifts out the received signal through the scan-out pin 515. Based on the resultant data, it is determined whether or not there is any fault, thereby testing the semiconductor integrated circuit 510.
In the semiconductor integrated circuit and the testing method thereof according to the first prior art example, a plurality of pre-designed functional blocks (e.g., macro cells) are combined and reused to increase the efficiency in designing. However, if the first and second functional blocks 501 and 502 are combined and reused, it might be difficult for the user to produce test data patterns that should be propagated through the respective functional blocks. This is because the user is not acquainted with the internal configurations and operations of the functional blocks. Also, if the circuit sizes of the first and second functional blocks 501 and 502 are huge, then it is extremely complicated and very difficult to produce test data patterns that should be propagated through the respective functional blocks.
Also, the semiconductor integrated circuit and the testing method thereof according to the second prior art example require a shift operation to propagate the test data patterns through respective functional blocks. Thus, a large number of clock cycles should be consumed for that purpose, and it is difficult to supply the test data patterns rapidly and continuously enough to detect a fault promptly.
In view of the foregoing respects, a first object of the present invention is to make a test easily executable among functional blocks even if the user does not know much about the internal configurations and operations of the functional blocks combined or if the circuit sizes of the functional blocks are enormous. A second object of the present invention is to make the signal propagation delay fault between the functional blocks readily testable.
A first IC functional block according to the present invention achieves the first object and includes a test data output circuit for outputting test data responsive to a control signal indicating a test data transmission state.
According to the first IC functional block, a test data output circuit for outputting test data is provided within the IC functional block. Thus, if a semiconductor integrated circuit is constructed of the block and another IC functional block including a circuit that can receive the test data and compare it to an expected value, then the test data can be transmitted and received even when the user does not know much about the internal configuration and operation of the IC functional blocks. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks can be carried out easily and accurately in the semiconductor integrated circuit.
In the first IC functional block, the test data output circuit preferably includes a plurality of output signal lines enabling parallel output, and preferably outputs the test data such that an adjacent pair of the output signal lines have mutually different values. In such an embodiment, when a semiconductor integrated circuit including the first IC functional block is tested, a shortcircuit fault in a signal line, which interconnects IC functional blocks together, can be detected with a lot more certainty.
In the first IC functional block, the test data output circuit preferably outputs the test data changing from one value into the other. Then, the second object is accomplished. And in a semiconductor integrated circuit composed of a plurality of IC functional blocks, a fault between the IC functional blocks, e.g., a signal transition from 0 into 1 or from 1 into 0 in a time exceeding a predetermined delay time, can be detected.
In the first IC functional block, the test data output circuit preferably includes a plurality of output signal lines enabling parallel output, and preferably outputs the test data such that an adjacent pair of the output signal lines have mutually different values, and that each of the output signal lines outputs the test data alternately changing from one value into the other and vice versa. In such an embodiment, when a semiconductor integrated circuit including the first IC functional block is tested, test data with mutually different values, e.g., 0 and 1, can be output through an adjacent pair of output signal lines. In addition, the values of the output signal can also be changed alternately on the time axis, e.g., from 0 into 1 and then from 1 into 0. Accordingly, an adjacent pair of signal lines can be tested more accurately as to a crosstalk between an adjacent pair of output signal lines, for example.
In the first IC functional block, the test data output circuit preferably includes a plurality of output signal lines enabling parallel output, divides the output signal lines into a number 2n of groups (where n is an integer equal to or larger than one) and outputs the test data such that the respective groups divided have mutually different values, which change from one value into the other. In such an embodiment, the second object is accomplished. And if a semiconductor integrated circuit including the first IC functional block is tested with the divisor n increased one by one every time until each group is no longer divisible, then a fault resulting from the interference by an adjacent signal line, e.g., delay or crosstalk, can be detected with more certainty from any combination of adjacent output signal lines. That is to say, there is no need to consider a combination of adjacent output signal lines in advance.
In the first IC functional block, the test data output circuit preferably includes: an original data generating section for generating and outputting first and second original data, the first original data being composed of zeros and ones alternately arranged, the second original data being obtained by inverting the first original data; and a selector circuit for receiving the first and second original data and selecting either the first or second original data in response to a selection signal externally supplied, thereby outputting the test data. In such an embodiment, when a semiconductor integrated circuit including the first IC functional block is tested, test data, in which a signal and an inverted signal thereof appear alternately and repeatedly, can be generated with more certainty. And if a plurality of selector circuits are provided such that the first and second original data are alternately selected by adjacent pairs of output signal lines, then test data, in which a signal and an inverted signal thereof appear alternately and repeatedly, can be generated in the adjacent pairs of output signal lines with more certainty.
In the first IC functional block, the test data output circuit preferably includes a plurality of selector circuits, and preferably further includes a shift register for receiving the selection signal and outputting the input selection signal to each said selector circuit. In such an embodiment, the number of selection signal lines can be cut down to one. Accordingly, the area of an interconnection line for the selection signal, which is provided outside, can be reduced and no burden is constituted on the interconnection region.
In the first IC functional block, the test data output circuit preferably includes: an original data generating section for generating and outputting original data composed of zeros and ones alternately arranged; and a plurality of inverter circuits, each receiving the original data. Control signals with mutually inverted values are preferably input to the inverter circuits, which output the test data with mutually inverted values. In such an embodiment, test data, where one signal and an inverted signal thereof are alternately arranged, can be generated without providing an interconnection for the inverted version of the original data. In addition, such test data, where one signal and an inverted signal thereof are alternately arranged, can also be generated for an adjacent pair of output signal lines. Accordingly, since it is not necessary to provide an interconnection for the inverted version of the original data, no burden is constituted on the circuit size.
In the first IC functional block, the test data output circuit preferably further includes a shift register for receiving the control signal and outputting the input control signal to each said inverter circuit.
In the first IC functional block, the test data output circuit preferably includes: a plurality of test data generating sections for generating mutually different test data; and a test data selecting section for selecting one of the test data generating sections responsive to the control signal. In such an embodiment, when a semiconductor integrated circuit including the first IC functional block is tested, optimum data for testing can be selectively output from a plurality of mutually different test data. As a result, the efficiency in testing can be improved.
The first IC functional block preferably further includes a decision result output circuit for receiving the test data responsive to a control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision. In such an embodiment, when a semiconductor integrated circuit including a plurality of first IC functional blocks is tested, it is possible to specify not only at least one of the IC functional blocks, which should receive the test data, but also the testing interval of each of the IC functional blocks. Accordingly, the accuracy of testing per IC functional block can be improved.
The first IC functional block preferably further includes a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state. In such an embodiment, when a semiconductor integrated circuit including a plurality of first IC functional blocks is tested, one of the IC functional blocks can be in test data transmission state, while at the same time another IC functional block can be in testing standby state. Thus, even if a signal line is shared in common between blocks, it is possible to prevent the test data from colliding against each other on the signal line. As a result, testing can be performed between the blocks more accurately.
In the first IC functional block, the test data output circuit preferably includes an inverted data generating section for inverting a value of the test data responsive to the control signal indicating the testing standby state. In such an embodiment, in testing a semiconductor integrated circuit, where a plurality of first IC functional blocks are used and one of the IC functional blocks shares an output signal line in common with another IC functional block, the former IC functional block can be in test data transmission state, while at the same time the latter IC functional block can be in testing standby state. Accordingly, the inverted data generating section of the latter IC functional block outputs the inverted version of the test data, which has been output from the former IC functional block, to its output section, the output of which is being blocked (e.g., in high impedance state). Thus, if there is any fault in the output section of the latter IC functional block, the inverted version of the test data is output from the output section of the latter IC functional block to an output signal line, which is shared with the former IC functional block, so as to collide against the test data output from the former IC functional block. As a result, if there is any abnormality in the test data from the former IC functional block during the testing thereof, then that abnormality can be observed by the IC functional block on the receiving end with more certainty.
The first IC functional block preferably further includes: a decision result output circuit for receiving the test data responsive to a control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision; and a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state.
A second IC functional block according to the present invention includes a decision result output circuit for receiving test data responsive to a control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision.
According to the second IC functional block, a decision result output circuit for receiving test data and deciding whether the test data received is correct or erroneous is provided within the IC functional block. Thus, if a semiconductor integrated circuit is constructed of the block and another IC functional block including a circuit that can output the test data, then the test data can be transmitted and received even when the user does not know much about the internal configuration and operation of the IC functional blocks. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks can be carried out easily and accurately in the semiconductor integrated circuit.
In the second IC functional block, the decision result output circuit preferably includes a plurality of expected value comparing sections, each comparing the test data to an expected value of the test data. In such an embodiment, even if a plurality of mutually different test data are received while a semiconductor integrated circuit including the second IC functional block is being tested, the decision can be performed correctly.
In the second IC functional block, the decision result output circuit preferably outputs the decision result on deciding that the test data is erroneous. In such an embodiment, as soon as the second IC functional block has received abnormal test data, which is different from the expected value thereof, while a semiconductor integrated circuit including the second IC functional block is being tested, the presence/absence of the fault can be estimated outside of the functional block.
In the second IC functional block, the decision result output circuit preferably includes holding means for holding the decision result thereon. In such an embodiment, while a semiconductor integrated circuit including the second IC functional block is being tested, it is possible to determine whether or not there is any fault by monitoring, from the outside of the functional block, a decision result signal, indicating that the second IC functional block has received abnormal test data, either when the testing ends or every time a predetermined interval has passed. Accordingly, batch processing can be carried out for the testing purposes.
In the second IC functional block, the holding means is preferably a shift register. In such an embodiment, even if the decision result signal is found to be a bit pattern as a result of monitoring the decision result signal from the outside of the functional block, the bit pattern of the decision result signal can be output in its entirety without getting the decision result signal stuck at one-bit information representing only the presence or absence of a fault. Accordingly, the test data received can be monitored in detail on a bit-by-bit basis. Furthermore, since the number of output pins required is only one, no burden is constituted on the interconnection region.
The second IC functional block preferably further includes a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state.
A third IC functional block according to the present invention includes a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state.
According to the third IC functional block, a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state is provided within the IC functional block. Thus, if a semiconductor integrated circuit is constructed of the block and another IC functional block including a circuit that can output the test data and a decision result output circuit for deciding whether the test data received is correct or erroneous, then testing can be performed between these blocks more accurately. This is because it is possible to prevent the test data from colliding against each other on a signal line that is shared between the blocks. As a result, the test data can be transmitted and received even when the user does not know much about the internal configuration and operation of the IC functional blocks. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks can be carried out easily and accurately in the semiconductor integrated circuit.
A semiconductor integrated circuit according to the present invention accomplishes the first and second objects. The semiconductor integrated circuit includes: a first functional block including a test data output circuit for outputting test data responsive to a first control signal indicating a test data transmission state; a second functional block for integrated circuit, including a decision result output circuit for receiving the test data responsive to a second control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision; a test control output section for outputting the first and second control signals to the first and second IC functional blocks, respectively; and a test result output circuit for receiving a decision result signal from the decision result output circuit and outputting the received decision result signal as a test result signal.
In the semiconductor integrated circuit according to the present invention, by externally operating the test control output section, the test data can be output from the first IC functional block and can be received by the second IC functional block, in which it is decided whether the test data is correct or erroneous by comparing it to its expected value. And the result of the decision can be monitored from the outside. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks, of which the semiconductor integrated circuit is made up, can be carried out easily and accurately.
The semiconductor integrated circuit of the present invention preferably further includes: an output signal line including a plurality of signal paths interconnecting the first and second IC functional blocks together; and a switching circuit, which is connected to the output signal line, for switching the signal paths by selecting one of the signal paths. The test data output circuit preferably outputs a path control signal for controlling the switching circuit. In such an embodiment, even if the output signal line interconnecting the first and second IC functional blocks together is designed to have a plurality of signal paths, the respective signal paths of the output signal line can be tested with more certainty.
In the semiconductor integrated circuit of the present invention, the test result output circuit preferably outputs the test result on receiving the decision result. In such an embodiment, as soon as the IC functional block has received abnormal test data, which is different from the expected value thereof, the presence/absence of a fault can be estimated outside of the semiconductor integrated circuit.
In the semiconductor integrated circuit of the present invention, the test result output circuit preferably includes holding means for holding the decision result thereon. In such an embodiment, it is possible to determine whether or not there is any fault by monitoring, from the outside of the semiconductor integrated circuit, a decision result signal, indicating that the IC functional block has received abnormal test data, either when the testing ends or every time a predetermined interval has passed. Accordingly, batch processing can be carried out for the testing purposes.
The semiconductor integrated circuit of the present invention preferably further includes a third IC functional block, including a testing standby circuit for blocking the output of an output signal responsive to a third control signal indicating a testing standby state. And the test control output section preferably outputs the third control signal to the third IC functional block. In such an embodiment, even if an inter-block signal line is shared in common between the third and first IC functional blocks, it is possible to prevent the signals from colliding against each other, because the third IC functional block is made to enter a standby state. As a result, the inter-block signal line can be tested more accurately.
The semiconductor integrated circuit of the present invention preferably further includes: an output signal line including a plurality of signal paths interconnecting one of the first, second and third IC functional blocks to the other ones; and a switching circuit, which is connected to the output signal line, for switching the signal paths by selecting one of the signal paths. The test data output circuit preferably outputs a path control signal for controlling the switching circuit.
The semiconductor integrated circuit of the present invention preferably includes a plurality of the second IC functional blocks. Each said second IC functional block preferably includes a shift register for holding the decision result thereon. And the shift registers are preferably connected together to constitute a single shift register. In such an embodiment, even if the decision result signal is found to be composed of a plurality of bit patterns as a result of monitoring the decision result signal from the outside of the semiconductor integrated circuit, all the bit patterns of the respective IC functional blocks, which are waiting for the output of the decision result, can be output continuously by coupling the first shift registers together and without getting the decision result signal stuck at one-bit information representing only the presence or absence of fault. Accordingly, the test data received can be monitored in detail on a bit-by-bit basis. Furthermore, since the number of output pins required is only one, no burden is constituted on the interconnection region.
A method for testing a semiconductor integrated circuit according to the present invention accomplishes the first and second objects. The semiconductor integrated circuit includes: a first functional block including a test data output circuit for outputting test data responsive to a first control signal indicating a test data transmission state; a second functional block for integrated circuit, including a decision result output circuit for receiving the test data responsive to a second control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision; a third functional block for integrated circuit, including a testing standby circuit for blocking the output of an output signal responsive to a third control signal indicating a testing standby state; a test control output section for outputting the first, second and third control signals to the first, second and third IC functional blocks, respectively; and a test result output circuit for receiving a decision result signal from the decision result output circuit and outputting the received decision result signal as a test result signal. The method includes: a test data transmitting step for making the test control output section output the first control signal to make the test data output circuit of the first IC functional block output the test data; a test data receiving step for making the test control output section output the second control signal to make the decision result output circuit of the second IC functional block, which is connected to the first IC functional block, receive the test data; a testing standby step for making the test control output section output the third control signal to make the testing standby circuit of the third IC functional block, which is connected to the first IC functional block, block the output; and a test result reading step for reading the test result from the test result output circuit.
In the method for testing a semiconductor integrated circuit according to the present invention, the connection between the first and second IC functional blocks can be tested by making the first IC functional block enter test data transmission state and the second IC functional block, which is connected to the first IC functional block, enter test data reception state, respectively. And at the same time, the third IC functional block is made to enter standby state. Thus, it is possible to prevent the signal, supplied from the third IC functional block, from colliding against the test data. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks, which the semiconductor integrated circuit is made up of, can be carried out easily and accurately.
In the method for testing a semiconductor integrated circuit according to the present invention, the test data output circuit preferably includes a plurality of output signal lines enabling parallel output. The test data transmitting step preferably includes: an initial signal line dividing step for dividing the output signal lines into two groups and outputting the test data through the output signal lines such that the respective groups divided have mutually different values, which change from one value into the other; a signal line dividing step for dividing each said group into two groups and outputting the test data through the output signal lines such that the respective groups divided have mutually different values, which change from one value into the other; and a testing step for repeatedly performing the signal line dividing step until the output signal line belonging to each said group is no longer divisible. In such an embodiment, the second object is accomplished. First, the IC functional blocks are divided into two groups in the initial signal line dividing step, and test data with mutually different values, e.g., 0 and 1, are output through the pair of groups adjacent to each other. In addition, the test data is output to change alternately on the time axis, e.g., from 0 into 1 or from 1 into 0. And if testing is performed as in the initial signal line dividing step with the divisor increased one by one every time until each group is no longer divisible, then a fault resulting from the interference by an adjacent signal line, e.g., delay or crosstalk, can be detected from any combination of adjacent output signal lines. That is to say, there is no need to consider a combination of adjacent output signal lines in advance.
A method for designing a semiconductor integrated circuit according to the present invention is adapted to design a semiconductor integrated circuit using a plurality of IC functional blocks. Each said IC functional block performs a predetermined function of a logic or memory circuit. The method includes: a functional block designing step for introducing, into each of the IC functional blocks, at least one of a test data output circuit for outputting test data responsive to a control signal indicating a test data transmission state, a decision result output circuit for receiving the test data responsive to a control signal indicating a test data reception state, deciding whether the test data received is correct or erroneous, and outputting a result of the decision and a testing standby circuit for blocking the output of an output signal responsive to a control signal indicating a testing standby state; a functional block library forming step for forming a library of functional blocks by registering the IC functional blocks, which have been made in the functional block designing step, at the library; and a functional block selecting step for selecting such an IC functional block as enabling a desired semiconductor integrated circuit from the IC functional blocks that are included in the library of functional blocks.
In the method for designing a semiconductor integrated circuit according to the present invention, the first through third IC functional blocks and semiconductor integrated circuit according to the present invention can be implemented just as designed.
Also, a testing-dedicated functional block for integrated circuit, which is made up of only the test data output circuits or decision result output circuits and does not include any circuits performing a predetermined function such as a logic or memory circuit, may be built. And a semiconductor integrated circuit may be constructed by combining the testing-dedicated functional block for integrated circuit with an IC functional block including the circuits with a predetermined function. Then, the connection between the IC functional blocks including the circuit with a predetermined function can be tested without increasing the circuit size thereof.
As described above, in the functional block for integrated circuit, semiconductor integrated circuit using the IC functional block, and respective methods for testing and designing the semiconductor integrated circuit according to the present invention, the number of steps of generating test data can be reduced in designing a semiconductor integrated circuit using IC functional blocks, which are combined or have an internal configuration about which much isn""t known or have a large circuit size. Accordingly, a test among the IC functional blocks, of which a semiconductor integrated circuit is made up, can be carried out easily and accurately. As a result, semiconductor integrated circuits are obtained with the fraction defective thereof reduced.